An efficient usage of a data processing system directly affects the consumption of resources that are necessary for its operation. Particularly, power consumption benefits from an efficient usage of CPU cores. Therefore, there it is recognized in the art that there is a need in the field to use a sufficient, not superfluous number of CPU cores when processing data packets in a multi-core system.
The required number of CPU cores is determined by the quantity of packets that have to be processed in unit time (processing rate). Since the quantity of data packets being processed may vary widely, there is a need to monitor such variations and adjust the number of cores correspondingly.
There are two conventional approaches to solving the problem of adjusting the number of processors: horizontal scaling, wherein it is the number of processing means that is being adjusted, and vertical scaling, wherein it is the computing power of one or more processors that is being adjusted.
A conventional device for data packet switching and server load balancing, described in U.S. Pat. No. 6,272,522 B1, is provided by a general-purpose multiprocessor computer system. The general-purpose multiprocessor computer system comprises a plurality of symmetrical processors coupled together by a common data bus, a main memory shared by the processors, and a plurality of network interfaces each adapted to be coupled to respective external networks for receiving and sending data packets via a particular communication protocol, such as Transmission Control Protocol/Internet Protocol (TCP/IP) and User Datagram Protocol (UDP). A first one of the processors is adapted to serve as a control processor and remaining ones of the processors are adapted to serve as data packet switching processors. The data packet switching processors are each coupled to at least one of the plurality of network interfaces. The control processor receives raw load status data from the external networks and generates load distribution configuration data therefrom. The load distribution configuration data is stored in the main memory for access by the data packet switching processors. The switching processors route received ones of the data packets to a selected one of the external networks in accordance with information included in a header portion of the data packets and the load distribution configuration data. The switching processors perform periodic polling of corresponding ones of the network interfaces to detect a received one of the data packets therein. In addition, the switching processors re-write the routing information included in the header portion of the data packets to reflect the selected one of the external networks.
However, the solution described in the U.S. Pat. No. 6,272,522 B1 does not deal with the problem of an increased or decreased number of incoming data packets.
Another conventional solution, described in U.S. Pat. No. 9,396,154 (B2), discloses a system comprising a multi-core processor, a data buffer, a hardware accelerator, and an interrupt controller. The interrupt controller transmits a first interrupt signal to a first one of the cores based on a first hardware signal received from the hardware accelerator. The first core creates a copy of buffer descriptors (BD) of a buffer descriptor ring that correspond to the data packets in the data buffer in a first virtual queue and indicates to the hardware accelerator that the data packets are processed. If there are additional data packets, the interrupt controller transmits a second interrupt signal to a second core, which performs the same steps as performed by the first core. The first and the second cores simultaneously process the data packets associated with the BDs in the first and second virtual queues, respectively.
However, the solution described in the U.S. Pat. No. 9,396,154 B2 does not deal with the problem of an increased or decreased number of incoming data packets.
Yet another conventional solution described in the U.S. Pat. No. 8,346,999 B2 discloses a method for dynamically receiving queue balancing with high and low thresholds, the method comprising the following steps: assigning a network application to at least one first core processing unit, from among a plurality of core processing units; assigning a first receive queue to the first core processing unit, wherein the first receive queue is adapted to receive packet flow associated with the network application; defining a high threshold for the first receive queue; monitoring the packet flow in the first receive queue and comparing a packet flow level in the first receive queue to the high threshold; wherein if the packet flow level exceeds the threshold based on the comparing, generating a queue status message indicating that the packet flow level in the first queue has exceeded the queue high threshold; and generating, in response to the queue status message, a new core assignment to assign the network application to a second core processing unit.
However, the solution described in the U.S. Pat. No. 8,346,999 B2 deals only with assigning a specific application to another core, which would most likely result in an unequal load distribution and non-optimum core load, thus decreasing the method efficiency.